The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a vertical channel transistor.
The size of cells integrated on a substrate is becoming smaller as semiconductor devices are becoming highly integrated. A transistor in a gigabyte dynamic random access memory (DRAM) device generally requires a size of approximately 4F2, wherein F represents the minimum feature size. Thus, vertical channel transistor has been introduced as a way to increase the efficiency of cells by increasing the integration scale of a DRAM device as well as securing the channel length of the transistor. The vertical channel transistor includes a transistor in which a channel is formed in a direction extending upward and downward, that is, in a vertical direction, with a surround type vertical gate enclosing an active pillar which is vertically extended over a substrate.
FIG. 1A illustrates a plan view of a semiconductor device including a typical vertical channel transistor. FIG. 1B illustrates cross-sectional views of the semiconductor device shown in FIG. 1A taken along lines X-X′ and Y-Y′.
Referring to FIGS. 1A and 1B, a plurality of pillar structures 13 are formed over a substrate 11. Each of the pillar structures 13 includes a stack structure of an active pillar 11A and a hard mask layer 12. Vertical gates 15 are formed to enclose lower sidewalls of the active pillars 11A. Buried bit lines 17 are formed in the substrate 11 by performing an ion implantation process. The buried bit lines 17 are isolated from each other by trenches 18. Gate insulation layers 14 are formed between the vertical gates 15 and the active pillars 11A. Passivation layers 16 are formed over sidewalls of the pillar structures 13 including the vertical gates 15 along a second direction, i.e., along the direction of the line Y-Y′. Second inter-layer insulation layers 19B are formed in the trenches 18. First inter-layer insulation layers 19A are formed between the pillar structures 13 where word lines 20 are not formed. Reference denotation 19 represents inter-layer insulation layers 19 including the first inter-layer insulation layers 19A and the second inter-layer insulation layers 19B.
In this typical method, a damascene word line (DWL) process is used to form the word lines 20 coupling adjacent vertical gates 15 as illustrated in FIG. 2.
FIG. 2 illustrates cross-sectional views of a typical damascene word line process. The cross-sectional views are taken along the lines X-X′ and Y-Y′ of the semiconductor device shown in FIG. 1A.
A damascene word line process includes isolating the buried bit lines 17 using the trenches 18, forming the second inter-layer insulation layers 19B buried between the pillar structures 13, and etching the second inter-layer insulation layers 19B to form damascene patterns 21. The word lines 20 shown in FIG. 1B are to be buried over the damascene patterns 21.
However, considering the gap-fill characteristic and property of matter such as hardness, the first inter-layer insulation layers 19A include borophosphosilicate glass (BPSG) and the second inter-layer insulation layers 19B include a spin on dielectric (SOD) layer in the typical method. Also, the passivation layers 16 include a nitride-based layer to reduce conductive impurities contained in the first inter-layer insulation layers 19A, e.g., phosphorus (P), from penetrating into the active pillars 11A.
In the typical method, portions of the passivation layers 16 exposed by the damascene patterns 21 are removed after the damascene patterns 21 are formed. The passivation layers 16 are removed using phosphoric acid. However, the inter-layer insulation layers 19 may be damaged by phosphoric acid.
To be specific, as shown in FIG. 3, the first inter-layer insulation layers 19A may collapse in a padding region by phosphoric acid, causing bridges to form at the end of the word lines 20 in the padding region. The reason is because the first inter-layer insulation layers 19A including BPSG is more damaged by phosphoric acid than the second inter-layer insulation layers 19B including SOD.
In order to overcome such a limitation, a technology which forms the first inter-layer insulation layers 19A using a SOD layer like that of the second inter-layer insulation layers 19B has been suggested. However, if the thickness of the remaining first inter-layer insulation layers 19A is different from one side of the pillar structures 13 to the other along the first direction, i.e., the direction along the line X-X′, due to a misalignment which may be generated during an etching process of the first inter-layer insulation layers 19A for forming the trenches 18, a stress imbalance may occur between the pillar structures 13 and the first inter-layer insulation layers 19A. Such stress imbalance may not cause much limitation if the first inter-layer insulation layers 19A are formed to include BPSG. However, if the first inter-layer insulation layers 19A are formed to include a SOD layer, the pillar structures 13 may bend as shown in FIG. 4. The reason is because SOD has a greater intra-layer stress than BPSG.